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Writer's picturerehsd
Apr 65 min read

Xilinx XC7Z020-1CLG484I (Zynq-7000 SoC, Artix-7 FPGA)

Updated: Jun 24

Recently, I have been working on different MCU and FPGA development boards. The FPGAs to this this point have been simpler, or older, FPGAs, such as Lattice iCE40 and Xilinx Spartan-3. I would eventually love to get to the point of a Zynq-7000 SoC / Artix-7 FPGA solution. With this goal, I have picked up a handful of Xilinx XC7Z020-1CLG484I ICs. This is a huge jump in complexity for me, from adding DDR memory to a BGA package with 484 balls to a much higher requirement for the PCB design!


I have previously worked with the Digilent Arty Z7: Zynq-7000 SoC Development Board which uses the XC7Z020-1CLG400C. For example, I built a 16-bit processor (based on Ben Eater's 8-bit breadboard CPU) with HDMI output; see Building a 16-bit CPU on an Arty Z7-20 (rehsdonline.com). I am hoping to develop my own development board, similar to the Digilent board. I will update this post as I work through the design(s), PCB revisions, etc. I recognize that I have a large learning curve with this project, but I like to set high goals for myself. As with all of my projects, I am very interested in any feedback or guidance any of you may offer!


Design Goals

  • First, and foremost, my goal is simply to learn. I may make design choices that allow me to practice something new to me, even if the latest and greatest approach to something may be different.

  • I would like to keep the design limited to a 100mm x 100mm PCB, primarily for PCB cost containment. I have no idea of how many layers will be needed yet, but I am guessing eight layers, possibly ten layers.

  • My plan is to leverage JLCPCB for manufacturing. I have had good results with them historically. They do have limitations when it comes to PCBs like the one in this project, so I will do my best to work with these constraints.

  • I will be using EasyEDA Pro for the design work. This tool choice seems to stress some people, and I'm not quite sure why. I have found it to be plenty capable. KiCad is an option, of course, but I have not seen anything KiCad can do that EasyEDA Pro cannot do (at least for things with which I am concerned). I figure any tool has pros and cons, and for the time being, I plan to stick with EasyEDA Pro.

  • I look to use parts that are generally available through suppliers like DigiKey, Mouser, and LCSC.


Specs

Specifications of the IC I am using:

  • Dual-core ARM Cortex-A9 MPCore™ with CoreSight™, 667 MHz

  • 256 KB on-chip memory

  • Support for DDR3, DDR3L, DDR2, LPDDR2

  • Artix-7 FPGA logic equivalent with 85K logic cells, 53.2K LUTs, 106.4K flip-flops, 4.9Mb block RAM, 220 DSP slices

  • Package: 484-CSPBGA / CLG484 (19mm x 19mm with 0.8mm pitch)

  • 128 PS I/O (Processing System), 200 High Range I/O (1.2V to 3.3V)


Misc. Design Ideas / Plans

  • Power (primary): PS56628 6A buck regulator ($1.70 x4). 4.5V to 18V input, 0.76V to 5.5V output. 8-HSOIC PowerPAD.

  • Power (alternate): AOZ6606PI 6A buck regulator ($0.75 x4). 4.5V to 18V input, down to 0.8V output. 8-SOIC.

  • DRAM (option 1): Micron MT41K256M16TW-107:P 256Mx16 4Gb DDR3L.

  • DRAM (option 2): ISSI IS43TR16256B-125KBL 512Mx8, 256Mx16 4Gb DDR3.

  • DRAM (option 3): Kingston D2516ECMDXGJD-U.

  • USB Bridge: FTDI FT2232H.

  • USB Transceiver: Microchip USB3320C-EZK.

  • Ethernet: Realtek RTL8211F-CG.

  • QSPI: W25Q128JV.

  • The rest is to be determined at this stage.


Chunking Through It

Below, I will post videos of progress as I go. I plan to work through the design iteratively, meaning that as I learn more I will continue to update previous work. To be clear, I do not have knowledge for all aspects of this project as I set out, but I plan to learn as I go. My first focus is getting the schematic right. I will likely put down placeholder components and in time properly wire up those components. I will also update the PCB as I go -- more for getting an idea of what the PCB space and general layout might look like. I do not plan to worry about PCB layers, power distribution, routing, or other PCB-related matters until the schematic has significantly progressed. My backlog of reading for this project is gigantic, and I'm working to digest it as rapidly as possible. I am also working through some FEDEVEL courses, which have been great.


Here are some high-level targets I have set for myself. I may find that these are unrealistic, but I need to start with something. :)


  • Schematic substantially complete: End of May

  • PCB design substantially complete: End of July

  • First revision PCB ordered in August, assembly in September.

  • Verilog work starting in October.










Following are the schematics and PCB layer prints, as of the time of the video above (part 7). As I mention in the video, I have a lot of work to do to verify the schematics, do trace length matching, and generally improve what's done so far.








More to come!





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