I have started the assembly of my VGA card for my 65816 PC. In this running post, I will share my updates as I work through assembly, testing, and initial coding. This is a continuation of 65816 PC Build - Lessons Learned and 65816+VGA Progress Update.
Brief Recap
I am working on a video card design targeting 320x240x1B (RRRGGGBB). I am using dual-port RAM, allowing relative independence of timing between the 65816 microprocessor and the video card circuit. Initial testing of circuit design seemed to be going OK, so I designed a PCB in an ISA add-in card form factor. I intend to use this add-in card in my 65816 PC.
The PCB design includes a main board for the video timing and output. Video RAM (dual-port SRAM) is added via stackable daughter cards. While the design can support up to four daughter cards, each with a pair of 32Kx8 SRAMs, my 65816 PC implementation will use two daughter cards (giving me 128KB of video RAM for memory-mapped I/O, sprites, etc.).
Board Population
I have completed the initial population of the three PCBs for 65816 video card.
Initial Fire Up
LCD syncs at 640x480. No video output. Issues found:
Center stack header on daughter cards had pins backwards (i.e., messed up pinouts to the rest of the memory circuit). I'll need to fix with some trace cuts and bodge wire.
One of the ICs I used from the EasyEDA library had no power connected in the underlying model. I mentioned this in my motherboard write-up -- don't trust user-submitted components in the EasyEDA library!
Updates
I am now getting some video output, but it's ugly. Something is way off. I'm double-checking all signal runs, scoping the signals, etc.
I sorted out the initial signal issues by triple-checking, and adjusting any incorrectly-placed, CS/OEB signals. I have connected a single SRAM to the video card to focus on ensuring the basic card functions as expected. I can add in the daughter cards with additional RAM once I stabilize the operation of the video card itself. I am now able to draw the first portion of the screen, based on a single SRAM.
I am losing proper sync signal after a period of time (see Sync Signal Issue below).
I have resolved the sync signal stability issue. I ended up swapping out the SN74AHC74N with an SN74AC74PC. In the process, I changed my sync logic on my PLDs, and I am seeing an improvement in the quality of the first pixel of each row.
I have two populated daughter cards installed with proper enable signals.
Full video output of 320x240 is working! I am running the 65816 at 6 MHz; any faster and I lose the ability to write to the video RAM. As the processor without the video card runs fine at 14 MHz, I'm hoping this is something I can clean up. Maybe signal integrity issues on the address/data bus?
I have ordered version 1.1 of the daughter card. In this version, I have corrected the pinout of the central stacking pins. I have also ordered version 1.1 of the motherboard, with corrected ISA slot pinouts.
I have started working on color calibration: VGA for 65816: Start of Color Calibration.
First run at moving content: VGA for 65816: First Run at Moving Content.
Next Steps
I believe the sync logic on the PLDs can be improved.
General signal and output quality improvements.
Test some moving content.
Version 1.1 Daughter Card
Updated design files have been posted to rehsd/PC-65816: PC based on 65816 (github.com).
Sync Signal Issue (resolved)
I am seeing that the sync signals become unstable after a short period of time. If I monitor the output of any of the HQx or VQx signals, they all look good to start. After a minute or two, the frequency of the output frequency drops, sometimes by 10%, sometimes by more.
I'm wondering if this is an issue with the SR latch design used in my PLDs in the sync circuits. Helmut Neemann suggested in this post that SR latches without a clock are very sensitive to hazards and that the circuit could become very fragile and unreliable; that matches the current symptoms. 🙃
So, I'm thinking I'll try to update the current PLD SR latch design to a clocked D-latch and see if that helps.
Update: I removed the SR latches from the timing logic. The sync stability issue is still present. However, I notice an improvement with the first pixel output. I believe this is due to me triggering an end of row slightly sooner with the logic below. I still have work to do on the vertical timing logic in the image below.
Update: I swapped out the SN74AHC74N in my pixel clock circuit with an SN74AC74PC. Stability issues are now gone.
Update: I spent some time working on the PLD logic for sync signals. I was getting good output on my LCD, but my VGA capture device didn't show an identical image. For example, in my capture software, the image would be pushed to the right a bit. After some trial and error, I have my LCD and VGA capture showing identical images. The logic I used is below. At this point, I don't intend to further modify this logic.
LCD monitor image and VGA capture device print screen below. I have the LCD monitor set to fill the screen with the image, so it's a slightly wider aspect ratio due to this stretching. Also, the LCD monitor picture was taken directly in front. If I take the picture from a slightly elevated position, it's brighter, and the colors look better (and more accurate). See VGA for 65816: Start of Color Calibration.
My To Do List
Rotate central dual-pin header on daughter cards. ✔
Move 74273 and resistors closer to VGA connector. ✔
Optimize pull-up/down resistors (e.g., different values, placement?).
Further refine sync logic on PLDs. ✔
Improve silkscreen labels.
Test card in updated motherboard, in slot closest to 65816.
M/S should be pulled high on the RAM ICs. I had them floating. Pulling high removed some artifacting I was seeing.
Add inline resistors to HSync and VSync outputs. (?)
Experiment: blend low bits of red and green into blue output.
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